The present invention relates to an inexpensive, high accuracy digital to analog converter for converting a digital input signal into a substantially proportional analog signal to be used in various types of communication systems and control equipments.
Various proposals for fabricating a digital to analog converter (hereafter referred to as a DAC) in the form of an integrated circuit (IC) have been made. For example, Holloway et al, have proposed "A High Yield Second Generation 10 Bit Monolithic DAC" in 1976, IEEE, ISSCC, pp. 106-107, in February, 1976. In an integrated circuit, it is easy to make the matching tolerances of elements mounted on the same chip relatively small. Therefore, the integrated circuit is suitable for fabrication of the DAC. On the other hand, it is impossible in the IC to replace the elements once fabricated by a new element or elements or to adjust a specific element or elements. Therefore, there is a limit to improving the accuracy of the DAC. The accuracy of the DAC is 12 bits at most, if no calibration is provided, in the present state of technology in this techanical field.
An analog trimming technique for directly adjusting element values has been proposed, as one approach to improving the DAC accuracy. The analog trimming technique successfully realizes 13- to 14-bit accuracy but requires an increased number of process steps for trimming components, an increased number of external pins, a complicated trimming process designed trimming device. In this respect, this approach is not advantageous from an economical viewpoint.
Another approach which has recently been proposed is a digital trimming technique for digitally calibrating total accuracy without any analog trimming of components. The approach aims at realizing the analog trimming process by means of logic circuits including ROM, RAM, digital adder and the like, which can easily be realized in the form of an IC. The approach by the digital trimming method is advantageous in that an economical IC construction is employed and the digital trimming does not require specially designed electrical devices.
In order to improve the non-linearity error of the DAC, in the digital trimming method, an analog output satisfying the required linearity is selected from outputs of a DAC with high resolution but an insufficient linearity (referred to as an original DAC), and the digital input of the original DAC is stored in a proper memory in a manner such that the selected output signal is obtained. The digital input signal of the original DAC which is stored as a digital signal corresponding to the output level is read out to drive the DAC, so that a DAC with a satisfactory linearity but a lower resolution than the original DAC is constructed.
Normally, DAC errors arise primarily from variations in the values of the weighting elements at higher order bits due to manufacturing variability of the weighting elements. Let us consider a case where bits ranging from the least significant bit (LSB) to the Lth bit as counted from the LSB are correctly weighted so that there is no error in this bit ranging, but the bits from the (L+1)th bit to the most significant bit (MSB) are erroneously weighted so that a weighting error occurs. In this case, the transfer characteristic of the DAC has a large transition or a jump at a carry point from the Lth bit to the (L+1)th in the code of the input signal to the DAC. Thus, a conventional digital calibration technique for the DAC calibrates by adding or subtracting an analog quantity of a deviation from an ideal characteristic. To this end, an analog calibrating signal produced from an additional calibrating DAC is applied to an adder/subtractor for the calibration. The calibrating operation is digitally performed by storing the input code to the additional DAC and a control signal for the analog adder/subtractor into an ROM or RAM. An example of this type of DAC is disclosed in U.S. Pat. No. 3,995,266.
In this type of DAC, it is difficult to perform error correction of the analog adder/subtractor and this impossibility prevents a high accuracy of digital to analog conversion. Therefore, to improve the linearity, a high accuracy adder/subtractor and an additional DAC are required. Particularly, in order to obtain the analog addition/subtraction function, a polarity inverting circuit and a control circuit for addition/subtraction are required. This makes it difficult to improve the accuracy and to reduce the chip area.